Center for Co-design of Chip, Package, System

The Center for Co-design of Chip, Package, System conducts leading-edge research in the following areas:
   • System Architecture, Planning, Modeling and Implementation
   • IC Floor Planning, Place & Route, Design, Modeling and Characterization
   • Advanced Packaging, Substrate Fabrication, Modeling and Characterization
   • Advanced Interconnect and 3D Integration Technologies
   • Electronic Design Automation that includes Physical CAD and Multi-physics Modeling
   • Emerging Device and Interconnect Technologies

The center is organized into program specific areas where a group of faculty with complimentary expertise work on application driven technologies. An overview of the programs can be found on our research page.

Center News

IEEE Transactions on Components, Packaging, and Manufacturing Technology Names New Editor-In-Chief

IEN congratulates Muhannad Bakir on being named as the editor-in-chief for the Electronics Manufacturing section of the IEEE Transactions on Components, Packaging, and Manufacturing Technology. This publication is the flagship journal for anything related to advanced packaging, 2.5D and 3D integrated circuit technologies, and heterogeneous integration.  

Professor Bakir leads the Integrated 3D Systems Group in the School of ECE and is a member of the Georgia Tech Center for Co-design of Chip, Package, System (C3PS).


Congratulations to Saibal Mukhopadhyay - Elevated to IEEE Fellow

ECE Professor, and C3PS Faculty Member, Professor Saibal Mukhopadhyay has been elevated to the level if IEEE Fellow “for contributions to energy-efficient and robust computing systems design”.Professor Saibal Mukhopadhyay received the bachelor of engineering degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India in 2000 and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in August 2006. Dr. Mukhopadhyay worked at IBM T. J. Watson Research Center, Yorktown Heights, N.Y. as research staff member from August 2006 to September 2007 and as an intern in summers of 2003, 2004, and 2005. At IBM, his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. He joined the faculty of the Georgia Institute of Technology in September 2007.

Join the CAEML and C3PS Team in Hangzhou China for the 2017 EDAPS Symposium!
December 14 - 16, 2017

Professors Swaminathan and Franzon to present a workshop on Machine Learning for Hardware Design

Full details and registration link available here.