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The Center for Co-design of Chip, Package, System conducts leading-edge research in the following areas:
• System Architecture, Planning, Modeling and Implementation
• IC Floor Planning, Place & Route, Design, Modeling and Characterization
• Advanced Packaging, Substrate Fabrication, Modeling and Characterization
• Advanced Interconnect and 3D Integration Technologies
• Electronic Design Automation that includes Physical CAD and Multi-physics Modeling
• Emerging Device and Interconnect Technologies
The center is organized into program specific areas where a group of faculty with complimentary expertise work on application driven technologies. An overview of the programs can be found on our research page.
Tom Sarvey Receives 2017 Best Paper Award for the IEEE Transactions on Components, Packaging, and Manufacturing Technology
Congratulations to Tom Sarvey on receiving the 2017 Best Paper Award for the IEEE Transactions on Components, Packaging, and Manufacturing Technology in the Components: Characterization and Modeling category. He will be recognized for the paper entitled "Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA” at the 2018 IEEE Electronic Components and Technology Conference. The conference will be held May 29-June 1 in San Diego, California.
This marks the second time that a member of the Integrated 3D Systems (I3DS) Group has won this particular Best Paper Award. Tom is a Ph.D. student in the I3DS Group, which is led by Muhannad Bakir. Tom’s coauthors on the paper are Yang Zhang, an alumnus of the group; Dr. Bakir; and Colman Cheung, Ravi Gutala, Arifur Rahman, and Aravind Dasu, all of Intel Corporation’s Programmable Solutions Group. For more than a decade, the challenge of removing the heat from high end computing platforms has been a primary limiter of processor power and computing performance. The use of micro-scale fluidic channels has previously been proposed as a method of extracting the large amounts of heat produced by modern processors. In this work, such a liquid-cooled heat sink was etched into the backside of a field programmable gate array (FPGA) die, approximately 500 μm from the heat generating circuitry. The heat sink, only 240 μm tall, provided a thermal resistance that is approximately one quarter of that of the best air-cooled heat sinks, in less than 1/1000th of the volume. This type of cooling has the potential to unlock higher computing throughput, lower energy usage, and denser integration in datacenters and high performance computing applications.
Jacob Smith Wins ECE Undergraduate Research Award
This award recognizes an undergraduate student who has demonstrated an unusually strong aptitude for research. Jacob will be recognized at the 2018 Roger P. Webb Awards Program in the School of Electrical and Computer Engineering on Tuesday afternoon, April 10, from 3:00-5:00 pm in the Klaus Building Atrium.