Tom Sarvey Receives 2017 Best Paper Award for the IEEE Transactions on Components, Packaging, and Manufacturing Technology
Congratulations to Tom Sarvey on receiving the 2017 Best Paper Award for the IEEE Transactions on Components, Packaging, and Manufacturing Technology in the Components: Characterization and Modeling category. He will be recognized for the paper entitled "Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA” at the 2018 IEEE Electronic Components and Technology Conference. The conference will be held May 29-June 1 in San Diego, California.
This marks the second time that a member of the Integrated 3D Systems (I3DS) Group has won this particular Best Paper Award. Tom is a Ph.D. student in the I3DS Group, which is led by Muhannad Bakir. Tom’s coauthors on the paper are Yang Zhang, an alumnus of the group; Dr. Bakir; and Colman Cheung, Ravi Gutala, Arifur Rahman, and Aravind Dasu, all of Intel Corporation’s Programmable Solutions Group. For more than a decade, the challenge of removing the heat from high end computing platforms has been a primary limiter of processor power and computing performance. The use of micro-scale fluidic channels has previously been proposed as a method of extracting the large amounts of heat produced by modern processors. In this work, such a liquid-cooled heat sink was etched into the backside of a field programmable gate array (FPGA) die, approximately 500 μm from the heat generating circuitry. The heat sink, only 240 μm tall, provided a thermal resistance that is approximately one quarter of that of the best air-cooled heat sinks, in less than 1/1000th of the volume. This type of cooling has the potential to unlock higher computing throughput, lower energy usage, and denser integration in datacenters and high performance computing applications.
Jacob Smith Wins ECE Undergraduate Research Award
This award recognizes an undergraduate student who has demonstrated an unusually strong aptitude for research. Jacob will be recognized at the 2018 Roger P. Webb Awards Program in the School of Electrical and Computer Engineering on Tuesday afternoon, April 10, from 3:00-5:00 pm in the Klaus Building Atrium.
News and Awards Archives
EDA’s CAEML Grows More Humps: Al Expands Role in Design
The use of AI in EDA is a hot topic due to significant progress with applying machine learning to the issues of chip design.
Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program. In the past, CAEML focused on signal integrity and power integrity, but this year, the team has diversified its portfolio with system analysis, chip layout and trusted platform design.
“One of the challenges we face is getting access to data from companies,” said Professor Madhavan Swaminathan, the John Pippin Chair in Microsystems Packaging & Electromagnetics and Director of Center for Co-Design of Chip, Package, System (C3PS) at the Georgia Institute of Technology, a CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”
Previously, the group had a sort of coming-out party. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.
After this year, it is clear that the EDA industry is entering its second phase in its use of AI (moving past high-speed interconnects, power delivery etc. and into the realm of machine learning), which the next phase of product development in optimizations that speed turnaround time. Often hindered by current algorithmic limitations.
Researchers are exploring opportunities to replace today’s simulators with AI models (faster) after a reported 40 MHz increase in speed last year. "Relatively slow simulators can lead to timing errors, mistuned analog circuits, and insufficient modeling that results in chip re-spins, said Swaminathan. In addition, machine learning can replace IBIS for behavioral modeling in high-speed interconnects."
Chip researchers are currently combatting the issue with research in data mining, surrogate models, statistical learning, and neural networking models (used by Amazon, Google etc).
“The amount of training data required is high,” said Christopher Cheng of Hewlett-Packard Enterprise, another member of the CAEML team. “Classifiers are static, but we want to add the dimension of time using recurrent neural networks to enable time-to-failure labels. We want to extend this work to more parameters and general system failures in the future.”
Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) partners with Notre Dame in $26 million multi-university research center developing next-generation computing technologies
In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.
With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).
Georgia Tech’s Center for Co-design of Chip, Package System (C3PS) led by Profs. A. Raychowdhury and M. Swaminathan, deputy director and director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.
The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.
Profs. Raychowdhury (PI) and Swaminathan (co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.
“Our involvement in the ASCENT center provides us with unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof. Raychowdhury, the ON Semiconductor Jr. Associate Professor of VLSI Systems.
“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”
This is one of the largest JUMP centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies. Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.
- Christa M. Ernst
Tushar Krishna Receives NSF CISE Research Initiation Initiative Award
Congratulations to Professor Tushar Krishna, ECE & C3PS, on receiving an NSF CISE Research Initiation Initiative Award. The title of his research project is “Enabling Neuroevolution in Hardware” and will be two years in duration.
Over the past few years, machine learning algorithms, especially neural networks (NN) have seen a surge of popularity owing to their potential in solving a wide variety of complex problems across image classification and speech recognition. Unfortunately, in order to be effective, NNs need to have the appropriate topology (connections between neurons) for the task at hand and have the right weights on the connections. This is known as supervised learning and requires training the NN by running it through terabytes to petabytes of data. This form of machine learning is infeasible for the emerging domain of autonomous systems (robots/drones/cars) which will often operate in environments where the right topology for the task may be unknown or keep changing, and robust training data is not available. Autonomous systems need the ability to mirror human-like learning, where we are continuously learning, and often from experiences rather than being explicitly trained. This is known as reinforcement learning.
The focus of this research will be on neuroevolution (NE), a class of reinforcement learning algorithms that evolve NN topologies and weights for the task at hand using evolutionary algorithms. The goal of this project will be on enabling NE in energy-constrained autonomous devices by leveraging opportunities for parallelism and hardware acceleration. If successful, this research can enable mass proliferation of autonomous drones and robots that can learn to perform tasks without being explicitly trained.
IEEE Transactions on Components, Packaging, and Manufacturing Technology Names New Editor-In-Chief
IEN congratulates Muhannad Bakir on being named as the editor-in-chief for the Electronics Manufacturing section of the IEEE Transactions on Components, Packaging, and Manufacturing Technology. This publication is the flagship journal for anything related to advanced packaging, 2.5D and 3D integrated circuit technologies, and heterogeneous integration.
Professor Bakir leads the Integrated 3D Systems Group in the School of ECE and is a member of the Georgia Tech Center for Co-design of Chip, Package, System (C3PS).
Congratulations to Saibal Mukhopadhyay - Elevated to IEEE Fellow
ECE Professor, and C3PS Faculty Member, Professor Saibal Mukhopadhyay has been elevated to the level if IEEE Fellow “for contributions to energy-efficient and robust computing systems design”.Professor Saibal Mukhopadhyay received the bachelor of engineering degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India in 2000 and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in August 2006. Dr. Mukhopadhyay worked at IBM T. J. Watson Research Center, Yorktown Heights, N.Y. as research staff member from August 2006 to September 2007 and as an intern in summers of 2003, 2004, and 2005. At IBM, his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. He joined the faculty of the Georgia Institute of Technology in September 2007.
Nasir Receives Best Paper Award at SRC TECHCON
Congratulations to Saad Bin Nasir for receiving the Best in Session Award at SRC TECHCON 2017, held Sept. 10-12, 2017 in Austin, Texas. Saad is currently a Ph.D. student working with Arijit Raychowdhury on digital and mixed-signal power management circuits. This is the second consecutive year that Saad has won the SRC TECHCON Best in Session Award in the area of power management circuits for SoCs.
Saad won the award in the Power Management track for his paper entitled, "A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-off”. This research brings together novel control techniques and their circuit implementations in reconfigurable hybrid linear regulators for wireline and wireless IO. The principal aim of this research is to demonstrate a four-way reconfigurable linear regulator exhibiting wide range PSR and energy-efficiency trade-off. The measured power supply rejection ranges from -9dB to -34dB and corresponding power-efficiency range from 87% to 56%. Parts of this ongoing research have been previously published in the International Solid State Circuits Conference, the Journal of Solid State Circuits, the IEEE Transactions on Power Electronics, the European Solid State Circuits Conference, and IEEE Custom Integrated Circuits Conference and have gained significant traction with SRC’s member companies.
Raychowdhury's Work on HyperFETs Garners IEEE Award
Congratulations to Arijit Raychowdhury on receiving the Best Paper Award from the IEEE Transactions on Multi-scale Computing Systems (TMSCS) for an article entitled "Enabling New Computation Paradigms with HyperFET.” It was published in 2016 and can be found in vol. 2, iss. 1, pp. 30-48 of the publication. This article was coauthored by collaborators from Penn State, the University of Notre Dame, and the University of Pittsburgh.
When augmented with traditional transistor technology (HyperFETs), phase transition devices can enable a vast class of computing primitives, from better transistors to oscillators and spike generators. Arijit and his colleagues have demonstrated through theory and experiments how HyperFETs can impact power efficiency of a class of computing architectures and applications. This work is currently being extended and explored in collaboration with Intel Corporation.
Arijit is currently the ON Semiconductor Associate Professor of ECE and leads the Integrated Circuits and Systems Research Lab. His students and he are exploring power-efficient circuits topologies and the corresponding computing models that can enable the next generation of low-power autonomous systems.
GT Team Looks to the Future of CHIPS with DARPA Program
A team of Georgia Tech researchers is bringing electronic design software and communications expertise to DARPA's new CHIPS initiative, which will enable future generations of integrated circuits to be assembled from plug-and-play modules known as “chiplets.” Reusing blocks of existing microelectronics technology could reduce the need to design complex monolithic chips from scratch for new applications.
“The goal of this program is to make the design more modular so we can reuse existing components, making the design process much faster, easier and cheaper,” said Sung Kyu Lim, a School of Electrical and Computer Engineering professor who heads up Georgia Tech’s part of the initiative. “We’ll be able to create new chips to meet specific needs by reusing these chiplets and putting them together in modular fashion. The modular design will allow us to pick and choose the components we need for specific applications.”
The four-year CHIPS effort involves 11 teams, including major defense contractors, microelectronics companies, design firms – and two other universities: the University of Michigan and North Carolina State University. In addition to Lim, the Georgia Tech effort will involve three other faculty members: Pippin Chair Professor Madhavan Swaminathan, Professor Saibal Mukhopadhyay and Assistant Professor Tushar Krishna, all from the School of Electrical and Computer Engineering.
Side-Channel Protection Research Scores Best Student Paper Award from IEEE - HOST
Saad Bin Nasir’s research into side-channel attack protection won the Best Student Paper Award at the 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), held May 1-5, 2017, in McLean, Virginia. This work is done in collaboration with the SPARC Lab, Purdue University (co-authors Debayan Das, Shovan Maity, and Shreyas Sen), and the Emerging Security Lab at Intel.
Saad is advised by ECE Associate Professor Arijit Raychowdhury. The paper is titled "High Efficiency Power Side-Channel Attack Immunity using Noise Injection in Attenuated Signature Domain”. Side-Channel Attacks (SCA) focus on measuring physical side-channel information leaked from computationally secure cryptographic engines to attack and expose a secret key. Power Side-Channel uses the power/current consumption of the cryptographic IC. This work proposes embedding the cryptographic engine in signature-attenuating dual-loop hardware (a novel shunt low-dropout regulator, LDO based on Switched Mode Control), along with tiny noise injection to demonstrate highly efficient protection against Power SCA. Modeling, test-chip development and testing were carried out in 130nm CMOS technology
New Research Program Puts the Flex in Electronics at GT
Suresh Sitaraman, Muhannad Bakir, Samuel Graham, Peter Hesketh, Manos Tentzeris, Chuck Zhang and Madhavan Swaminathan have been recognized by Georgia Tech with the Outstanding Achievement in Research Program Development Award for creating the Flexible Electronics Ecosystem – A Research, Development, Education, and Product Transition Program.
Hua Wang Named IEEE Outstanding Young Engineer
Congratulations to Prof. Hua Wang on being named as the 2017 Outstanding Young Engineer Award of the IEEE Microwave Theory and Techniques Society (MTT-S). This award is the highest honor for young IEEE MTT-S members (younger than 38 years of age) who have distinguished achievements in the Society’s fields of interest. Hua is being honored “for outstanding early career contributions to the microwave profession” and will receive this award at the 2017 IEEE MTT-S International Microwave Symposium, which will be held June 4-9, 2017, in Honolulu, Hawaii.