IEEE Transactions on Components, Packaging, and Manufacturing Technology Names New Editor-In-Chief
IEN congratulates Muhannad Bakir on being named as the editor-in-chief for the Electronics Manufacturing section of the IEEE Transactions on Components, Packaging, and Manufacturing Technology. This publication is the flagship journal for anything related to advanced packaging, 2.5D and 3D integrated circuit technologies, and heterogeneous integration.
Professor Bakir leads the Integrated 3D Systems Group in the School of ECE and is a member of the Georgia Tech Center for Co-design of Chip, Package, System (C3PS).
Congratulations to Saibal Mukhopadhyay - Elevated to IEEE Fellow
ECE Professor, and C3PS Faculty Member, Professor Saibal Mukhopadhyay has been elevated to the level if IEEE Fellow “for contributions to energy-efficient and robust computing systems design”.Professor Saibal Mukhopadhyay received the bachelor of engineering degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India in 2000 and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in August 2006. Dr. Mukhopadhyay worked at IBM T. J. Watson Research Center, Yorktown Heights, N.Y. as research staff member from August 2006 to September 2007 and as an intern in summers of 2003, 2004, and 2005. At IBM, his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. He joined the faculty of the Georgia Institute of Technology in September 2007.
News and Awards Archives
Nasir Receives Best Paper Award at SRC TECHCON
Congratulations to Saad Bin Nasir for receiving the Best in Session Award at SRC TECHCON 2017, held Sept. 10-12, 2017 in Austin, Texas. Saad is currently a Ph.D. student working with Arijit Raychowdhury on digital and mixed-signal power management circuits. This is the second consecutive year that Saad has won the SRC TECHCON Best in Session Award in the area of power management circuits for SoCs.
Saad won the award in the Power Management track for his paper entitled, "A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-off”. This research brings together novel control techniques and their circuit implementations in reconfigurable hybrid linear regulators for wireline and wireless IO. The principal aim of this research is to demonstrate a four-way reconfigurable linear regulator exhibiting wide range PSR and energy-efficiency trade-off. The measured power supply rejection ranges from -9dB to -34dB and corresponding power-efficiency range from 87% to 56%. Parts of this ongoing research have been previously published in the International Solid State Circuits Conference, the Journal of Solid State Circuits, the IEEE Transactions on Power Electronics, the European Solid State Circuits Conference, and IEEE Custom Integrated Circuits Conference and have gained significant traction with SRC’s member companies.
Raychowdhury's Work on HyperFETs Garners IEEE Award
Congratulations to Arijit Raychowdhury on receiving the Best Paper Award from the IEEE Transactions on Multi-scale Computing Systems (TMSCS) for an article entitled "Enabling New Computation Paradigms with HyperFET.” It was published in 2016 and can be found in vol. 2, iss. 1, pp. 30-48 of the publication. This article was coauthored by collaborators from Penn State, the University of Notre Dame, and the University of Pittsburgh.
When augmented with traditional transistor technology (HyperFETs), phase transition devices can enable a vast class of computing primitives, from better transistors to oscillators and spike generators. Arijit and his colleagues have demonstrated through theory and experiments how HyperFETs can impact power efficiency of a class of computing architectures and applications. This work is currently being extended and explored in collaboration with Intel Corporation.
Arijit is currently the ON Semiconductor Associate Professor of ECE and leads the Integrated Circuits and Systems Research Lab. His students and he are exploring power-efficient circuits topologies and the corresponding computing models that can enable the next generation of low-power autonomous systems.
GT Team Looks to the Future of CHIPS with DARPA Program
A team of Georgia Tech researchers is bringing electronic design software and communications expertise to DARPA's new CHIPS initiative, which will enable future generations of integrated circuits to be assembled from plug-and-play modules known as “chiplets.” Reusing blocks of existing microelectronics technology could reduce the need to design complex monolithic chips from scratch for new applications.
“The goal of this program is to make the design more modular so we can reuse existing components, making the design process much faster, easier and cheaper,” said Sung Kyu Lim, a School of Electrical and Computer Engineering professor who heads up Georgia Tech’s part of the initiative. “We’ll be able to create new chips to meet specific needs by reusing these chiplets and putting them together in modular fashion. The modular design will allow us to pick and choose the components we need for specific applications.”
The four-year CHIPS effort involves 11 teams, including major defense contractors, microelectronics companies, design firms – and two other universities: the University of Michigan and North Carolina State University. In addition to Lim, the Georgia Tech effort will involve three other faculty members: Pippin Chair Professor Madhavan Swaminathan, Professor Saibal Mukhopadhyay and Assistant Professor Tushar Krishna, all from the School of Electrical and Computer Engineering.
Side-Channel Protection Research Scores Best Student Paper Award from IEEE - HOST
Saad Bin Nasir’s research into side-channel attack protection won the Best Student Paper Award at the 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), held May 1-5, 2017, in McLean, Virginia. This work is done in collaboration with the SPARC Lab, Purdue University (co-authors Debayan Das, Shovan Maity, and Shreyas Sen), and the Emerging Security Lab at Intel.
Saad is advised by ECE Associate Professor Arijit Raychowdhury. The paper is titled "High Efficiency Power Side-Channel Attack Immunity using Noise Injection in Attenuated Signature Domain”. Side-Channel Attacks (SCA) focus on measuring physical side-channel information leaked from computationally secure cryptographic engines to attack and expose a secret key. Power Side-Channel uses the power/current consumption of the cryptographic IC. This work proposes embedding the cryptographic engine in signature-attenuating dual-loop hardware (a novel shunt low-dropout regulator, LDO based on Switched Mode Control), along with tiny noise injection to demonstrate highly efficient protection against Power SCA. Modeling, test-chip development and testing were carried out in 130nm CMOS technology
New Research Program Puts the Flex in Electronics at GT
Suresh Sitaraman, Muhannad Bakir, Samuel Graham, Peter Hesketh, Manos Tentzeris, Chuck Zhang and Madhavan Swaminathan have been recognized by Georgia Tech with the Outstanding Achievement in Research Program Development Award for creating the Flexible Electronics Ecosystem – A Research, Development, Education, and Product Transition Program.
Hua Wang Named IEEE Outstanding Young Engineer
Congratulations to Prof. Hua Wang on being named as the 2017 Outstanding Young Engineer Award of the IEEE Microwave Theory and Techniques Society (MTT-S). This award is the highest honor for young IEEE MTT-S members (younger than 38 years of age) who have distinguished achievements in the Society’s fields of interest. Hua is being honored “for outstanding early career contributions to the microwave profession” and will receive this award at the 2017 IEEE MTT-S International Microwave Symposium, which will be held June 4-9, 2017, in Honolulu, Hawaii.